A. Field of the Invention
The present invention relates to insulated gate semiconductor devices (hereinafter referred to as “IGBT's”).
B. Description of the Related Art
In exploring the developments of electric power converters that exhibit low electric power consumption, power devices that play a key role in the electric power converters have been expected to exhibit low electric power consumption. Among the power devices, insulated gate bipolar transistors (hereinafter referred to as “IGBT's”) are preferable to achieve a low ON-state voltage due to their conductivity modulation effects. Moreover, the IGBT's are controlled easily via their gate with a voltage applied thereto. Therefore, the use of the IGBT's has been established. The IGBT's may be classified into a planar IGBT and a trench IGBT. The planar IGBT includes gate electrodes formed along a chip surface. The trench IGBT includes gate electrodes buried in the respective trenches formed perpendicularly from a chip surface with an oxide film interposed between each gate electrode and the wall of the pertinent trench. The trench IGBT is more advantageous than the planar IGBT for increasing the channel density, since channels are formed in the side walls of the trenches. Therefore, the application fields for the trench IGBT are increasing.
Now the structure of the conventional trench IGBT as described above will be described in detail below with reference to FIG. 9. FIG. 9 shows a cross section of an n-channel IGBT including trench gates, the planar pattern of which includes stripes extending in parallel to each other. The cross section shown in FIG. 9 is cut perpendicular to the stripe-shaped trench gates.
Referring now to FIG. 9, a silicon wafer includes a lightly-doped n-type silicon substrate serving as drift layer 2-1, n+-type field stop layer 2-2 on a first surface of drift layer 2-1, and heavily-doped p-type thin collector layer 1-1, the impurity concentration of which is controlled, on field stop layer 2-2. A plurality of p-type base regions 3 are formed on a second surface of drift layer 2-1. In the surface portion of p-type base region 3, n+-type emitter regions 4 are formed selectively. Trench 20 is formed from the surface of n+-type emitter regions 4 to drift layer 2-1 through p-type base region 3. Gate electrode 6 made of electrically-conductive polycrystalline silicon is formed in trench 20 with gate oxide film 5 interposed between gate electrode 6 and the wall of trench 20. Interlayer insulator film 7 on trenches 20 insulates gate electrodes 6 from emitter electrode 8 formed on interlayer insulator film 7. Emitter electrode 8 is formed in such a manner that emitter electrode 8 is in electrical contact commonly with n+-type emitter regions 4 and p-type base regions 3 via windows formed through interlayer insulator film 7. Collector electrode 9 is formed on the back surface of p-type thin collector layer 1-1.
For bringing the trench IGBT shown in FIG. 9 into the ON-state, a voltage higher than the threshold voltage is applied to gate electrodes 6 in the state in which a voltage higher than the voltage applied to emitter electrode 8 is applied to collector electrode 9. As electric charges are accumulated to gate electrodes 6 by the voltage application described above, channels (not shown) inverted to the n-type are formed in the walls of p-type base regions 3 facing to respective gate electrodes 6 via gate oxide films 5. Electrons are injected from n+-type emitter regions 4 into drift layer 2-1 via the n-channels. The injected electrons bias collector junction 1-2 in forward and holes are injected from collector electrode 9, resulting in the ON-state of the trench IGBT. The voltage drop between collector electrode 9 and emitter electrode 8 in the resulting ON-state is the ON-state voltage.
For bringing the IGBT from the ON-state to the OFF-state, the voltage between emitter electrode 8 and gate electrode 6 is lowered below the threshold. By lowering the voltage, the electric charges accumulated in gate electrode 6 are discharged to a gate driver circuit via gate resistance. As the electric charges are discharged, the channel regions that have been inverted to the n-type return to the p-type, interrupting the electron path. Thus, the electron feed to drift layer 2-1 is interrupted. As the electron feed to drift layer 2-1 is interrupted, the hole feed from the collector side is also interrupted. Therefore, the electrons and holes accumulated in drift layer 2-1 are ejected to collector electrode 9 and emitter electrode 8, respectively, or recombine with each other. Thus, the electric current vanishes, bringing the IGBT to the OFF-state thereof.
Various improvements have been proposed to further lower the ON-state voltage of the trench IGBT. The injection enhanced gate bipolar transistor (hereinafter referred to as the “IEGT”) disclosed in Unexamined Japanese Patent Application Publication No. Hei. 5(1993)-243561 (FIG. 101), which is a counterpart of U.S. Pat. No. 5,329,142 (hereinafter referred to as “JP 1993-243561”) exhibits an extremely low ON-state voltage close to the ON-state voltage of the diode. The trench IEGT shown in FIG. 101 of JP 1993-243561 has a structure in which a part of the surface of an n+-type emitter region and a part of the surface of a p-type base region are covered with an insulator film such that the part of the emitter region and the part of the p-type base region are not in contact with an emitter electrode. The holes in the portion of the p-type base region not in contact with the emitter electrode are hardly ejected to the emitter electrode but liable to be accumulated. As a result, the carrier concentration distribution in an n-type drift layer is close to that in the diode. Therefore, the ON-state voltage of the disclosed trench IEGT can be set to be lower than the ON-state voltage of the trench IGBT. JP 1993-243561 names the effect which the disclosed trench IEGT exhibits an “IE effect.”
Power devices have been required to exhibit high-speed switching performances in addition to exhibiting a low ON-state voltage. It has been an important object for conventional IGBT's to improve their high-speed switching performances. However, since trench structures are formed very densely in conventional trench IGBT and trench IEGT, the capacitance between the gate electrode and the emitter electrode is liable to be larger than usual, impairing the switching performance. Therefore, it also is important to reduce the capacitance between the gate electrode and the emitter electrode, which causes impaired switching performances.
Now the IEGT shown in FIG. 1 of the Unexamined Japanese Patent Application Publication No. 2001-308327 (FIG. 1), which is a counterpart of U.S. Pat. No. 6,737,705 (hereinafter referred to as “JP 2001-308327”) will be described below with reference to FIG. 9 attached to the description of the present invention and equivalent to FIG. 1 of JP 2001-308327. The mesa region in the conventional IEGT, sandwiched by trench gates equivalent to those sandwiching region 11 in FIG. 9, is covered with an insulator film in the same manner as region 11 in FIG. 9. The mesa region potential floats in the same manner as the potential of region 11 in FIG. 9. (Here, “mesa” means “trapezoidal.”) The portion of the trench gate structure in the conventional IEGT covered with an insulator layer does not exhibit all the primary functions effectively in the same manner as the portion of the trench gate covered with an insulator layer in FIG. 9. Therefore, the capacitance between the gate electrode and the emitter electrode in the conventional IEGT is reduced as compared with the usual IGBT, and the trench gate structure thereof exhibits all the primary functions effectively. The conventional IEGT disclosed in JP 2001-308327 shortens the charging and discharging times and reduces the switching loss.
Yamaguchi et al. have reported that the IEGT disclosed in JP 2001-308327 has problems to be solved with respect to its turn-on characteristics (“IEGT Design Criterion for Reducing EMI Noise”, Proc. ISPSD 2004, pp. 115-119, 2004). The IEGT disclosed in JP 1993-243561 also has problems to be solved with respect to the turn-on characteristics. Therefore, it is a first object of the present invention to improve the turn-on characteristics.
It is essentially difficult for the IGBT shown in the above-described FIG. 9 to exhibit a high device breakdown voltage. The difficulty in obtaining a high device breakdown voltage poses a second problem for the IGBT shown in FIG. 9. Since the trenches are spaced apart from each other with unequal distances, the electric field distribution is liable to be nonuniform, causing electric field localization to the trench gate bottom. Therefore, the breakdown voltage of the IGBT shown in the FIG. 9 is liable to be lower.
To alleviate the first and second problems, Unexamined Japanese Patent Application Publication No. 2006-210547 (Abstract), which is a counterpart of U.S. Patent Application Publication No. US 2006/0163649 (hereinafter referred to as “JP 2006-210547”), and Unexamined Japanese Patent Application Publication No. 2000-228519 (FIGS. 6 and 7), which is a counterpart of U.S. Pat. No. 6,380,586 (hereinafter referred to as “JP 2000-210547”), disclose an IGBT, the perspective view of which is shown, for example, in FIG. 1 of the former document. The disclosed IGBT has a trench gate structure that includes trenches, the surface pattern of which includes a repetition of stripes extending in parallel to each other. The trenches dug in perpendicular to the semiconductor substrate surface are formed by etching the semiconductor substrate from its surface. The trench gate structure includes a gate electrode buried in each trench with an insulator film interposed between the gate electrode and the wall of the trench. The trench gate structure also includes p-type base regions and the extended portions of an n-type drift layer arranged alternately in the longitudinal direction of the semiconductor substrate surface between the trenches. In other words, the n-type drift layer extends between the p-type base regions between an adjacent pair of the trenches. The IGBT disclosed in these two documents and having the trench gate structure as described above exhibits a low ON-state voltage, low switching losses, improved turn-on characteristics, and a high breakdown voltage.
Now the IGBT disclosed in JP 2006-210547 will be described more in detail. The IGBT disclosed in JP 2006-210547 is characterized in that the mesa region thereof is connected to the emitter electrode via resistance to fix the mesa region potential so that the mesa region sandwiched by the trenches may not be a perfect floating region, the potential thereof is floating completely. The IGBT disclosed in JP 2006-210547, having the specific feature as described above, improves the turn-on characteristics thereof and obviates the first problem. As described in the above-described Yamaguchi et al., the potential of the mesa region in the floating state varies the gate potential in the process of turning-on. The gate potential variations destabilize the turn-on operation of the IGBT, causing problems in the controllability of the IGBT.
Removal of a floating region may be an essential measure for solving the above-described problem. However, if the floating region is simply removed, the usual IGBT, which does not exhibit any IE effect, will be obtained, causing a higher ON-state voltage. Therefore, a first measure of removing a floating region cannot be employed alone. So as not to impair the IE effect, it is necessary to use another measure together with removal of the floating region.
For example, the mesa region sandwiched between the trenches is divided into p-type regions and limited portions in the mesa region are provided with an emitter structure as a second measure. The second measure reduces the switching loss while suppressing the ON-state voltage of the trench IGBT as low as the ON-state voltage of the IEGT, and thus further reduces the total losses. If the first and second measures are employed together, the regions, in which the gate electrode faces the emitter structure, will decrease. Therefore, the electric field distributions in the base region and in the trench gate bottom will be nonuniform, further lowering the breakdown voltage of the device and impairing the reliability of the trench gate.
Therefore, it is necessary to employ a third measure to make the electric field distributions in the base region and in the trench gate bottom uniform in addition to the first and second measures. In detail, the n-type layer portion in the mesa region between the trench gates is set at a width narrow enough to be depleted easily by an applied voltage of several V to relax the electric localization to the trench gate bottom so that a high breakdown voltage may be obtained.
The IGBT disclosed in JP 2006-210547 and provided with the first through third measures facilitates making the electric field distribution near the surface of the device in the OFF-state thereof uniform and improving the breakdown voltage. Moreover, the IGBT disclosed in JP 2006-210547 and provided with the first through third measures facilitates reducing the capacitance between the gate electrode and the collector electrode. Thus, the IGBT disclosed in JP 2006-210547 and provided with the first through third measures also obviates the first and second problems.
However, the gate threshold voltage of the IGBT disclosed in JP 2006-210547 is liable to vary. This problem can be described in detail as follows. First, the structure of the IGBT disclosed in JP 2006-210547 will be described with reference to FIGS. 10-13. FIG. 10 is a perspective and cross sectional view of a trench IGBT taken in perpendicular to the wafer surface and trenches. FIG. 11 is a cross sectional view taken along line segment A-A of FIG. 10. FIG. 12 is a cross sectional view taken along line segment B-B of FIG. 10. FIG. 13 is a cross sectional view taken along line segment C-C of FIG. 10.
Referring now to these drawings, a silicon wafer includes heavily doped p-type collector layer 1-1, n+-type field stop layer 2-2, and lightly doped n-type drift layer 2-1. In the drift-layer-side surface portion of the silicon wafer, p-type base regions 3 are formed selectively. In p-type base region 3, n+-type emitter regions 4 are formed selectively. In FIG. 10, p-type base regions 3 are scattered such that p-type base regions 3 and the extended portions of lightly doped n-type drift layer 2-1 appear alternately in the longitudinal direction of trench 20. In the direction perpendicular to trenches 20, p-type base regions 3 are arranged such that p-type base regions 3 and the extended portions of lightly doped n-type drift layer 2-1 are positioned alternately with trench 20 interposed between base region 3 and the extended portion of drift layer 2-1. In the entire surface of the active region, in which an effective current flows, p-type base regions 3 are arranged in a staggered manner such that a checkered surface pattern is formed. It is preferable to arrange p-type base regions 3 in a staggered manner as described above, since p-type base regions 3 are distributed uniformly throughout the active region. The uniform distribution of p-type base regions 3 makes the electric field distribution uniform and prevents the IGBT from breakdown.
Trench 20 is filled with polycrystalline silicon gate electrode 6 working as a control electrode with gate oxide film 5 interposed between the wall of trench 20 and gate electrode 6. As shown in FIG. 11, a portion in the major surface of the silicon substrate, to which gate electrode 6 and drift layer 2-1 are extended, is covered with interlayer insulator film 7. On interlayer insulator film 7, emitter electrode 8 is formed such that emitter electrode 8 is in contact commonly with n+-type emitter region 4 and p-type base region 3. On the (back) surface of p-type collector layer 1-1, collector electrode 9 is formed. Since p-type base regions 3 are distributed in the surface of drift layer 2-1 between trenches 20 extended in parallel to each other, p-type base region 3 is expanded such that p-type base region 3 is diffused laterally only in the longitudinal direction of trench 20 from a window for ion implantation.
As shown in FIGS. 9-11, n+-type emitter regions 4 are disposed only adjacent to the trench side walls. Since the cross section B-B shown in FIG. 12 does not cut any n+-type emitter region 4, n+-type emitter region 4 is not shown in FIG. 12. In the cross section C-C shown in FIG. 13, n+-type emitter regions 4 are shown. In FIG. 10, the portion in which emitter electrode 8 is in contact commonly with n+-type emitter region 4 and p-type base region 3 is an emitter contact 10, illustrated by a shaded portion.
In the IGBT described in JP 2006-210547, p-type base regions 3, each shaped with a cell, are distributed in the active region surface. Therefore, electrons are injected radially from n+-type emitter region 4 in each cell to drift layer 2-1 via p-type base region 3 as illustrated by arrows 30 in FIG. 13. If the gate threshold voltage of a channel portion, on the most substrate-surface-side and designated by x, is lower than the gate threshold voltage of the other channel portions y, the gate threshold voltage of the entire semiconductor device will be determined by the channel portion x. In the portion x near to the substrate surface, the relative positional relation between the mesa region and the emitter region is liable to change. Since the peak concentration in the mesa region changes when the relative positional relation between the mesa region and the emitter region changes, the channel portion x is adversely affected easily by the gate threshold voltage deviating from the desired value and such causes. Therefore, the IGBT described in JP 2006-210547 causes a wider threshold voltage variation easily as compared with the IGBT described in JP 1993-243561.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide an insulated gate semiconductor device having a trench IGBT structure that distributes cell units having a trench gate structure throughout the active region and that can minimize threshold voltage variations.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.